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1 typical a pplica t ion fea t ures descrip t ion ultrathin 20v in , 3a step-down dc/dc module regulator the lt m ? 4623 is a complete 3a step-down switching mode module (micromodule) regulator in a tiny ultrathin 6.25mm 6.25mm 1.82mm lga package. included in the package are the switching controller, power fets, inductor and support components. operating over an input voltage range of 4v to 20v or 2.375v to 20v with an external bias supply, the LTM4623 supports an output voltage range of 0.6v to 5.5v, set by a single external resistor. its high efficiency design delivers 3a continuous output current. only ceramic input and output capacitors are needed. the LTM4623 supports selectable discontinuous mode operation and output voltage tracking for supply rail se - quencing. its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability . fault protection features include overvoltage, overcurrent and overtemperature protection. the LTM4623 is rohs compliant with pb free finish. 3a, 1.5v output dc/dc module ? step-down regulator 1.5v output efficiency vs load current a pplica t ions n <2mm height, complete solution in <1cm 2 (single-sided pcb) or 0.5cm 2 (dual-sided pcb) n wide input voltage range: 4v to 20v n input voltage down to 2.375v with external bias n 0.6v to 5.5v output voltage n 3a dc output current n 1.5% maximum total dc output v oltage error n current mode control, fast transient response n low emi en55022 class b compliant n external frequency synchronization n multiphase operation with current sharing n output voltage tracking n selectable discontinuous mode n power good indicator n overvoltage, overcurrent and overtemperature protection n ultrathin 6.25mm 6.25mm 1.82mm lga package n pcie and backside pcb mounting n telecom, datacom, networking and industrial equipment n data storage rack units and cards l , lt, ltc, ltm, module, linear technology and the linear logo are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 40.2k 4623 ta01a 10f 25v v in 4v to 20v v out 1.5v 3a 47f 6.3v 0.1f v in sv in run intv cc mode phmode track/ss freq v out fb pgood comp gnd sgnd LTM4623 clkin clkout load current (a) 0 efficiency (%) 80 85 90 3 4623 ta01b 75 70 60 0.5 1 2 1.5 2.5 65 95 v in = 5v v in = 12v LTM4623 4623f for more information www.linear.com/LTM4623
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , sv in .................................................... C0 .3v to 22v v out ................................................. C0 .3v to sv in or 6v run .......................................................... C 0.3v to sv in intv cc ...................................................... C0 .3v to 3.6v pgood, mode, track/ss, freq, phmode, clkin .................................. C 0.3v to intv cc internal operating junction temperature range (notes 2, 5) ............................................ C 40c to 125c storage temperature range .................. C 55c to 125c peak solder reflow body temperature ................. 245 c (note 1) (see pin functions, pin configuration table) lga package 25-lead (6.25mm 6.25mm 1.82mm) top view clkin sv in v in v out intv cc mode gnd a 5 1 2 3 4 sgnd freq phmode track/ss run b c d e clkout pgood fb comp t jmax = 125c, v jctop = 17c/w, v jcbottom = 11c/w, v jb + v ba = 22c/w, v ja = 22c/w, v ja derived from 95mm w 76mm pcb with 4 layers v values determined per jesd51-12, weight = 0.5g e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = sv in = 12v per the typical application shown on the front page. o r d er i n f or m a t ion symbol parameter conditions min typ max units v in input dc voltage sv in = v in l 4 20 v v out(range) output voltage range l 0.6 5.5 v v out(dc) output voltage, total variation with line and load c in = 22f, c out = 100f ceramic, r fb = 40.2k, mode = intv cc , i out = 0a to 3a (note 3) C40c to 125c l 1.477 1.50 1.523 v v run run pin on threshold v run rising 1.1 1.2 1.3 v i q(svin) input supply bias current v in = 12v, v out = 1.5v, mode = intv cc v in = 12v, v out = 1.5v, mode = gnd shutdown, run = 0, v in = 12v 6 2 11 ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 3a 0.5 a i out(dc) output continuous current range v in = 12v, v out = 1.5v 0 3 a v out (line)/v out line regulation accuracy v out = 1.5v, v in = 4v to 20v, i out = 0a l 0.04 0.15 %/v v out (load)/v out load regulation accuracy v out = 1.5v, i out = 0a to 3a l 0.5 1.5 % part number pad or ball finish part marking* package type msl rating temperature range (note 2) device finish code LTM4623ev#pbf au (rohs) LTM4623v e4 lga 3 C40c to 125c LTM4623iv#pbf au (rohs) LTM4623v e4 lga 3 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? pb-free and non-pb-free part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www .linear.com/packaging LTM4623 4623f for more information www.linear.com/LTM4623
3 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4623 is tested under pulsed load conditions such that t j t a . the LTM4623e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4623i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. symbol parameter conditions min typ max units v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, v in = 12v, v out = 1.5v 5 mv v out(start) turn-on overshoot i out = 0a, c out = 100f ceramic, track/ss = 0.01f, v in = 12v, v out = 1.5v 30 mv t start turn-on time c out = 100f ceramic, no load, track/ss = 0.01f, v in = 12v, v out = 1.5v 2.5 ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 80 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 40 s i outpk output current limit v in = 12v, v out = 1.5v 3.5 5 a v fb voltage at fb pin i out = 0a, v out = 1.5v, C40c to 125c l 0.592 0.60 0.606 v i fb current at fb pin (note 4) 30 na r fbhi resistor between v out and fb pins 60.05 60.40 60.75 k i track/ss track pin soft-start pull-up current track/ss = 0v 2 4 a v in(uvlo) v in undervoltage lockout v in falling, sv in = v in v in hysteresis, sv in = v in 2.4 2.6 350 2.8 v mv t on(min) minimum on-time (note 4) 40 ns t off(min) minimum off-time (note 4) 70 ns v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C15 7 C10 10 C7 15 % % i pgood pgood leakage 2 a v pgl pgood voltage low i pgood = 1ma 0.02 0.1 v v intvcc internal v cc voltage sv in = 4v to 20v 3.1 3.3 3.4 v v intvcc load reg intv cc load regulation i cc = 0ma to 20ma 0.5 % f osc oscillator frequency freq = open 1 mhz note 3: see output current derating curves for different v in , v out and t a . note 4: 100% tested at wafer level. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = sv in = 12v per the typical application shown on the front page. LTM4623 4623f for more information www.linear.com/LTM4623
4 typical p er f or m ance c harac t eris t ics dcm mode efficiency with 12v in, 1.5v out 1.5v output transient response 1.0v output transient response 1.2v output transient response 1.8v output transient response 2.5v output transient response efficiency vs load current with 5v in efficiency vs load current with 12v in efficiency vs load current with 16v in load current (a) 0 efficiency (%) 80 85 90 3 4623 g01 75 70 1 2 60 65 100 95 v out = 1.0v v out = 1.2v v out = 1.5v v out = 2.5v v out = 3.3v, 2mhz load current (a) 0 efficiency (%) 80 85 90 3 4623 g02 75 70 1 2 60 65 95 v out = 1.2v v out = 1.0v v out = 1.5v v out = 2.5v v out = 3.3v, 2mhz v out = 5v, 2mhz load current (a) 0 efficiency (%) 80 85 90 3 4623 g03 75 70 1 2 60 65 95 v out = 1.2v v out = 1.0v v out = 1.5v v out = 2.5v v out = 3.3v, 2mhz v out = 5v, 2mhz load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 0.1 1 4623 g03 0 dcm ccm v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.0v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g05 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.2v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g06 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.5v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g07 v in = 12v v out = 1.8v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g08 v out 50mv/div ac-coupled load step 1a/div v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 2.5v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g09 LTM4623 4623f for more information www.linear.com/LTM4623
5 short circuit with 3a load applied start-up with 3a load applied start-up with no load applied output ripple short circuit with no load applied 3.3v output transient response start into pre-biased output short circuit with 3a load applied 5v output transient response typical p er f or m ance c harac t eris t ics v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 3.3v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g10 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 5v freq = 1mhz output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4623 g11 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap soft start = 0.1f 5ms/div 4623 g12 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap soft start = 0.1f 5ms/div 4623 g13 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 5ms/div 4623 g14 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 20s/div 4623 g15 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 20s/div 4623 g16 v out 5mv/div ac-coupled v in = 12v v out = 5v freq = 1mhz input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 500ns/div 4623 g17 v in 2v/div v out 1v/div v in = 12v v out = 5v freq = 1mhz pre-biased v out = 2.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 500ns/div 4623 g18 pre-biased v out = 2.5v LTM4623 4623f for more information www.linear.com/LTM4623
6 p in func t ions comp (a1): current control threshold and error amplifier compensation point. the current comparators trip thresh - old is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v . t ie the comp pins together for parallel operation. the device is internally compensated. this is an output pin. do not force a voltage on this pin. track/ss (a2): output tracking and soft-start input. allows the user to control the rise time of the output volt - age. putting a voltage below 0.6v on this pin bypasses the internal reference input to the error amplifier, and ser vos the fb pin to match the track/ss voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifier. theres an internal 2a pull-up current from intv cc on this pin, so putting a capacitor here provides a soft-start function. run (a3): run control input of the switching mode regulator. enables chip operation by tying run above 1.2v. pulling it below 1.1v shuts down the part. do not leave floating. freq (a4): frequency is set internally to 1mhz. an ex - ternal resistor can be placed from this pin to sgnd to increase frequency , or from this pin to int v cc to reduce frequency. see the applications information section for frequency adjustment. fb (b1): the negative input of the error amplifier. internally, this pin is connected to v out with a 60.4k precision resis - tor. different output voltages can be programmed with an additional resistor between the fb and sgnd pins. tying the fb pins together allows for parallel operation. see the applications information section for details. phmode (b2): control input to phase selector of the switching mode regulator channel. this pin determines the phase relationship between internal oscillator and clkout signal. tie it to intv cc for 2-phase operation, tie it to sgnd for 3-phase operation, and tie it to intv cc /2 for 4-phase operation. gnd (b3, c3, d3-d4, e3): power ground pins for both input and output returns. sgnd (b4): signal ground connection. tie to gnd with minimum distance. connect freq resistor, comp com - ponent, mode, track/ss component, fb resistor to this pin as needed. v out (c1, d1-d2, e1-e2): power output pins. apply out - put load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. pgood (c2): output power good with open-drain logic. pgood is pulled to ground when the voltage on the fb pin is not within 10% of the internal 0.6v reference. mode (c4): operation mode select. tie this pin to intv cc to force continuous synchronous operation at all output loads. tying it to sgnd enables discontinuous mode operation at light loads. do not leave floating. sv in (c5): signal v in . input voltage to the on-chip 3.3v regulator. tie this pin to the v in pin in most applications. otherwise connect sv in to an external voltage supply of at least 4v which must also be greater than v out . v in (d5, e5): power input pins. apply input voltage be- tween these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. intv cc (e4): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. this pin is internally decoupled to gnd with a 1f low esr ceramic capacitor. clkin (a5): external synchronization input to phase detector of the switching mode regulator. this pin is internally terminated to sgnd with 20k. the phase-locked loop will force the top power nmoss turn-on signal to be synchronized with the rising edge of the clkin signal. clkout (b5): output clock signal for polyphase operation of the switching mode regulator. the phase of clkout with respect to clkin is determined by the state of the phmode pin. clkouts peak-to-peak amplitude is intv cc to gnd. this is an output pin. do not force a voltage on this pin. package row and column labeling may vary among module products. review each package layout carefully. LTM4623 4623f for more information www.linear.com/LTM4623
7 b lock diagra m decoupling r equire m en t s symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4v to 20v, v out = 1.5v) i out = 3a 4.7 10 f c out external output capacitor requirement (v in = 4v to 20v, v out = 1.5v) i out = 3a 22 47 f figure 1. simplified LTM4623 block diagram power control fb 60.4k 1f 0.1f r fb 40.2k 0.1f c in 10f intv cc v out mode track/ss run clkin clkout phmode comp 1f v out v in sv in 10k pgood v out 1.5v 3a v in 4v to 20v intv cc gnd 1h 4623 bd freq 162k internal comp sgnd internal filter c out 47f LTM4623 4623f for more information www.linear.com/LTM4623
8 o pera t ion the LTM4623 is a standalone nonisolated switch mode dc/ dc power supply. it can deliver up to 3a dc output current with few external input and output capacitors. this module provides precisely regulated output voltage adjustable between 0.6v to 5.5v via one external resistor over a 4v to 20v input voltage range. with an external bias supply above 4v connected to sv in , this module operates with an input voltage down to 2.375v. the typical application schematic is shown in figure 24. the LTM4623 contains an integrated constant on-time valley current mode regulator, power mosfets, inductor, and other supporting discrete components. the default switching frequency is 1mhz. for output voltages between 3.3v and 5.5v, an external 162k resistor is required between freq and sgnd pins to set the operating frequency to 2mhz to optimize inductor current ripple. for switching noise-sensitive applications, the switching frequency can be adjusted by external resistors and the module regulator can be externally synchronized to a clock within 30% of the set frequency. see the applications information section. with current mode control and internal feedback loop compensation, the LTM4623 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast cur - rent limiting. foldback current limiting is provided in an over current condition indicated by a drop in v fb reducing inductor valley current to approximately 40% of the origi - nal value. internal output overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. continuous operation is forced during ov and uv condition except during start-up when the track pin is ramping up to 0.6v. furthermore, in order to protect the internal power mosfet devices against transient voltage spikes, the LTM4623 constantly monitors the v in pin for an overvoltage condi - tion. when v in rises above 23.5v, the regulator suspends operation by shutting off both power mosfets. once v in drops below 21.5v, the regulator immediately resumes normal operation. the regulator does not execute its soft-start function when exiting an overvoltage condition. multiphase operation can be easily employed with the synchronization and phase mode controls. up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin to different levels. the LTM4623 has clkin and clkout pins for polyphase operation of multiple devices or frequency synchronization. pulling the run pin below 1.1v forces the controller into its shutdown state, turning off both power mosfets and most of the internal control circuitry. at light load currents, discontinuous mode (dcm) operation can be enabled to achieve higher efficiency compared to continu - ous mode (ccm) by pulling the mode pin to sgnd. the track/ss pin is used for power supply tracking and soft-start programming. see the applications informa- tion section. LTM4623 4623f for more information www.linear.com/LTM4623
9 a pplica t ions i n f or m a t ion the typical LTM4623 application circuit is shown in figure? 24. external component selection is primarily determined by the input voltage, the output voltage and the maximum load current. refer to table 7 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratios that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of the regulator . the minimum off-time limit imposes a maximum duty cycle which can be calculated as: d max = 1 C (t off(min) ? f sw ) where t off(min) is the minimum off-time, typically 70ns for LTM4623, and f sw (hz) is the switching frequency. conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as: d min = t on(min) ? f sw where t on(min) is the minimum on-time, typically 40ns for LTM4623. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. note that additional thermal derating may be applied. see the thermal considerations and output current derating section in this data sheet. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor connects the v out and fb pins together. adding a resistor, r fb , from fb pin to sgnd programs the output voltage: r fb = 0.6v v out ? 0.6v ? 60.4k table 1. r fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 r fb (k) open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 pease note that for 3.3v and 5v output, a higher operating frequency (2mhz) is required to optimize inductor current ripple. see operating frequency section. for parallel operation of n-channels LTM4623, tie all the fb pins together and use the following equation to solve for r fb : r fb = 0.6v v out C 0.6v ? 60.4k n input decoupling capacitors the LTM4623 module should be connected to a low ac impedance dc source. for the regulator, a 10f input ceramic capacitor is required for rms ripple current de - coupling. bulk input capacitance is only needed when the input sour ce impedance is compromised by long inductive leads, traces or not enough sour ce capacitance. the bulk capacitor can be an aluminum electrolytic capacitor or polymer capacitor. without considering the inductor ripple current, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1?d ( ) where % is the estimated efficiency of the power module. output decoupling capacitors with an optimized high frequency, high bandwidth design, only a single low esr output ceramic capacitor is required for the LTM4623 to achieve low output ripple voltage and very good transient response. additional output filter - ing may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 7 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 1a load-step transient. the linear t echnology ltpowercad? design tool is available to download online for output ripple, stability and transient response analysis for further optimization. discontinuous current mode (dcm) in applications where low output ripple and high efficiency at intermediate current are desired, discontinuous current mode (dcm) should be used by connecting the mode pin LTM4623 4623f for more information www.linear.com/LTM4623
10 a pplica t ions i n f or m a t ion to sgnd. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. forced continuous current mode (ccm) in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to intv cc . in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4623s output voltage is in regulation. operating frequency the operating frequency of the LTM4623 is optimized to achieve the compact package size and the minimum out- put ripple voltage while still keeping high efficiency. the default operating frequency is internally set to 1mhz. in most applications, no additional frequency adjusting is required. if any operating frequency other than 1mhz is required by application, the operating frequency can be increased by adding a resistor, rfset, between the freq pin and sgnd, as shown in figure 28. the operating frequency can be calculated as: f hz ( ) = 1.6e11 161k||r fset ( ) to reduce switching current ripple, 2mhz operating fre - quency is required for 3.3v to 5.5v output with r fset ?=?161k to sgnd. the operating frequency can also be decreased by adding a resistor between the freq pin and intv cc , calculated as: f hz ( ) = 1mhz ? 2.8e11 r fset ( ) the programmable operating frequency range is from 800khz to 4mhz. frequency synchronization and clock in the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the external clock frequency range must be within 30% around the set operating frequency. a pulse detection circuit is used to detect a clock on the clkin pin to turn on the phaselocked loop. the pulse width of the clock has to be at least 100ns. the clock high level must be above 2v and clock low level below 0.3v. during the start-up of the regulator, the phase-locked loop function is disabled. multiphase operation for output loads that demand more than 3a of current, multiple LTM4623s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. the clkout signal can be connected to the clkin pin of the following LTM4623 stage to line up both the frequency and the phase of the entire system. tying the phmode pin to intvcc, sgnd or intv cc /2 generates a phase differ - ence (between clkin and clkout) of 180, 120, or 90 respectively , which corresponds to 2-phase, 3-phase or 4-phase operation. a total of 12 phases can be cascaded to run simultaneously out of phase with respect to each other by programming the phmode pin of each LTM4623 to different levels. figure 2 shows a 4-phase design and a 6-phase design example for clock phasing. table 2. phmode pin status and corresponding phase relationship (relate to clkin) phasmd intv cc sgnd intv cc /2 clkout 180 120 90 a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by , the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). LTM4623 4623f for more information www.linear.com/LTM4623
11 the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. the LTM4623 device is an inherently current mode con - trolled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. please tie the run, track/ss, fb and comp pins of each paralleling module together. figure 26 shows an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure?3 shows this graph. a pplica t ions i n f or m a t ion figure 2. 4-phase, 6-phase operation figure 3. rms input ripple current to dc load current ratio as a function of duty cycle 0.75 0.8 4623 f03 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty factor (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1 phase 2 phase 3 phase 4 phase 6 phase 4623 f02 clkin phmode clkout 0 90 180 270 +90 +90 +90 phase 4 phase 3 phase 2 phase 1 intv cc /2 intv cc /2 intv cc /2 intv cc /2 clkin phmode clkout clkin phmode clkout clkin phmode clkout clkin phmode clkout 120 240 (420) 60 180 +120 +180 +120 phase 4 phase 2 phase 5 intv cc intv cc phase 3 clkin phmode clkout clkin phmode clkout clkin phmode clkout 300 +120 phase 6 clkin phmode clkout 0 phase 1 clkin phmode clkout +120 LTM4623 4623f for more information www.linear.com/LTM4623
12 a pplica t ions i n f or m a t ion soft-start and output voltage tracking the track/ss pin provides a means to either soft start the regulator or track it to a different power supply. a capacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 2a current source will charge up the external soft-start capacitor towards intv cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 2a where c ss is the capacitance on the track/ss pin. cur- rent foldback and forced continuous mode are disabled during the soft-start process. output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 4 and figure 5 show an example waveform and schematic of ratiometric tracking where the slave regulators output slew rate is proportional to the masters. since the slave regulators track/ss is connected to the masters output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6v, the slave output voltage and the master output voltage should satisfy the following equation during start-up: v out(sl) ? r fb(sl) r fb(sl) +60.4k = v out(ma) ? r tr(bot) r tr(top) +r tr(bot) figure 4. output ratiometric tracking waveform figure 5. example schematic of ratiometric output voltage tracking time slave output master output output voltage 4623 f04 freq clkin clkout v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd r fb(ma) 40.2k LTM4623 10f 16v v in 4v to 15v v out(ma) 1.5v 3a 47f 6.3v c ss r tr(bot) 40.2k r fb(sl) 60.4k r tr(top) 60.4k freq v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd 4623 f05 LTM4623 10f 16v v out(sl) 1.2v 3a 47f 6.3v clkin clkout LTM4623 4623f for more information www.linear.com/LTM4623
13 a pplica t ions i n f or m a t ion the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure 5. following the previous equation, the ratio of the masters output slew rate (mr) to the slaves output slew rate (sr) is determined by: mr sr = r fb(sl) r fb(sl) +60.4k r tr(bot) r tr(top) +r tr(bot) for example, v out(ma) =1.5v, mr = 1.5v/1ms and v out(sl) = 1.2v, sr = 1.2v/1ms. from the equation, we could solve that r tr(top) = 60.4k and r tr(bot) = 40.2k are a good combination for the ratiometric tracking. the track/ss pin will have the 2a current source on when a resistive divider is used to implement tracking on the slave regulator. this will impose an offset on the track/ss pin input. smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track/ss pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking in which the masters output slew rate (mr) is the same as the slaves output slew rate (sr), waveform as shown in figure 6. figure 6. output coincident tracking waveform from the equation, we could easily find that, in coincident tracking, the slave regulators track/ss pin resistor divider is always the same as its feedback divider: r fb(sl) r fb(sl) +60.4k = r tr(bot) r tr(top) +r tr(bot) for example, r tr(top) = 60.4k and r tr(bot) = 60.4k is a good combination for coincident tracking for a v out(ma) = 1.5v and v out(sl) = 1.2v application. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin is pulled low when the output voltage exceeds a 10% window around the regulation point. to prevent unwanted pgood glitches during transients or dynamic v out changes, the LTM4623s pgood falling edge includes a blanking delay of approximately 52 switching cycles. stability compensation the LTM4623s internal compensation loop is designed and optimized for use with low esr ceramic output capacitors. table 7 is provided for most application requirements. in case more phase margin is required for the application, an additional 100pf feedforward capacitor (c ff ) can be placed between the v out and fb pins. the ltpowercad design tool is available for control loop optimization. run enable pulling the run pin to ground forces the LTM4623 into its shutdown state, turning off both power mosfets and most of its internal control circuitry. bringing the run pin above 0.7v turns on the internal reference only, while still keeping the power mosfets off. increasing the run pin voltage above 1.2v will turn on the entire chip. low input application the LTM4623 module has a separate sv in pin which makes it suitable for low input voltage applications down to 2.375v. the sv in pin is the single input of the whole control circuitry while the v in pin is the power input which directly connects time master output slave output output voltage 4623 f06 LTM4623 4623f for more information www.linear.com/LTM4623
14 a pplica t ions i n f or m a t ion to the drain of the top mosfet. in most applications where v in is greater than 4v, connect sv in directly to v in with a short trace. an optional filter, consisting of a resistor (1 to 10) between sv in and v in along with a 0.1f bypass capacitor between sv in and ground, can be placed for ad - ditional noise immunity. this filter is not necessary in most cases if good pcb layout practices are followed (see figure 23). in a low input voltage application (2.375v to 4v), connect sv in to an external voltage higher than 4v with 1f local bypass capacitor. in some cases, switching frequency also needs to be reduced to keep a minimum 0.8a peak-to-peak inductor current ripple by adding a resistor from intv cc pin to freq pin. see operating frequency section. figure 25 shows an example of a low input voltage application. please note the sv in voltage cannot go below the v out voltage. pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the LTM4623 can safely power up into a pre-biased output without discharging it. the LTM4623 accomplishes this by forcing discontinuous mode (dcm) operation until the track/ss pin voltage reaches 0.6v reference voltage. this will prevent the bg from turning on during the pre-biased output start-up which would discharge the output. please do not pre-bias LTM4623 with a voltage higher than intv cc (3.3v) voltage or a voltage higher than the output voltage set by the feedback resistor (r fb ). overtemperature protection the internal overtemperature protection monitors the junction temperature of the module. if the junction temperature reaches approximately 160c, both power switches will be turned off until the temperature drops about 15c cooler. radiated emi noise high radiated emi noise is a disadvantage for switching regulators by nature. fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4623 inte - grates the feature to minimize the radiated emi noise to meet the most applications with low noise requirements. it is fully compliant with the en55022 class b standard. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd 51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in jesd 51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulators thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are, in and of themselves, not relevant to providing guidance of thermal per formance; instead, the derating cur ves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased next: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. LTM4623 4623f for more information www.linear.com/LTM4623
15 a pplica t ions i n f or m a t ion 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages, but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure 7; blue resistances are contained within the module regulator , whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the LTM4623 be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laborator y testing in a controlled environment chamber to reasonably define and correlate the thermal resistance figure 7. graphical representation of jesd 51-12 thermal coefficients 4623 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance LTM4623 4623f for more information www.linear.com/LTM4623
16 a pplica t ions i n f or m a t ion values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the LTM4623 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jsed 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the LTM4623 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due diligence yields the set of derating curves shown in this data sheet. after these laboratory tests have been performed and correlated to the LTM4623 model, then the jb and ba are summed together to provide a value that should closely equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. the 1.0v, 1.5v, 3.3v and 5v loss curves in figures?8 to 11 can be used in coordination with the load current derating curves in figures 12 to 22 for calculating an approximate ja thermal resistance for the LTM4623 with various air - flow conditions. the power loss curves are taken at room temperature, and are increased with a multiplicative factor according to the ambient temperature. this approximate factor is: 1.3 for 120c at junction temperature. maximum load current is achievable while increasing ambient tem - perature as long as the junction temperature is less than 120c, which is a 5c guard band from maximum junction temperature of 125c. when the ambient temperature reaches a point where the junction temperature is 120c, then the load current is lowered to maintain the junction at 120c while increasing ambient temperature up to 120c. the derating curves are plotted with the output current starting at 3a and the ambient temperature at 30c. the output voltages are 1.0v, 1.5v, 3.3v and 5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measure - ments in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air flow . the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example, in figure 16 the load current is derated to 2.5a at ~95c with no air flow or heat sink and the power loss for the 12v to 1.5v at 2.5a output is about 1.0w. the 1.0w loss is calculated with the ~0.8w room temperature loss from the 12v to 1.5v power loss curve at 2.5a in figure 9, and the 1.3 multiplying factor at 120c junction temperature. if the 95c ambient temperature is subtracted from the 120c junction temperature, then the difference of 25c divided by 1.0w equals a 25c/w ja thermal resistance. table 4 specifies a 25c/w value which is very close. table 3 to t able 6 provide equivalent thermal resistances for 1.0v to 5v outputs with and without air flow. the derived thermal resistances in table 3 to table?6 for the various condi - tions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the ef - ficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multiplicative factors. the printed cir cuit board is a 1.6mm th ick 4-layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. safety considerations the LTM4623 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and overcurrent protection. LTM4623 4623f for more information www.linear.com/LTM4623
17 figure 8. 1.0v output power loss figure 9. 1.5v output power loss figure 10. 3.3v output power loss a pplica t ions i n f or m a t ion figure 14. 16v to 1v derating curve, no heat sink figure 12. 5v to 1v derating curve, no heat sink figure 11. 5v output power loss figure 13. 12v to 1v derating curve, no heat sink figure 15. 5v to 1.5v derating curve, no heat sink load current (a) 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4623 f08 1 2 3 power loss (w) v in = 16v v in = 12v v in = 5v load current (a) 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4623 f09 1 2 3 power loss (w) v in = 16v v in = 12v v in = 5v load current (a) 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4623 f10 1 2 3 power loss (w) v in = 16v v in = 12v v in = 5v figure 16. 12v to 1.5v derating curve, no heat sink load current (a) 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4623 f11 1 2 3 power loss (w) v in = 16v v in = 12v ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f12 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f13 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f14 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f15 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f16 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm LTM4623 4623f for more information www.linear.com/LTM4623
18 a pplica t ions i n f or m a t ion table 3. 1.0v output, no heat sink derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 12, 13, 14 5, 12, 16 figure 8 0 none 25 figures 12, 13, 14 5, 12, 16 figure 8 200 none 22 figures 12, 13, 14 5, 12, 16 figure 8 400 none 22 table 4. 1.5v output, no heat sink derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 15, 16, 17 5, 12, 16 figure 9 0 none 25 figures 15, 16, 17 5, 12, 16 figure 9 200 none 22 figures 15, 16, 17 5, 12, 16 figure 9 400 none 22 figure 17. 16v to 1.5v derating curve, no heat sink figure 18. 5v to 3.3v derating curve, no heat sink figure 19. 12v to 3.3v derating curve, no heat sink figure 21. 12v to 5v derating curve, no heat sink figure 20. 16v to 3.3v derating curve, no heat sink figure 22. 16v to 5v derating curve, no heat sink ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f17 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 120 4623 f18 40 60 100 130 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 4623 f25 40 60 100 120 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 4623 f26 40 60 100 120 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 4623 f27 40 60 100 120 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 30 3.5 3 2.5 2 1.5 1 0.5 0 80 4623 f28 40 60 100 120 90 50 70 110 derated load current (a) 0lfm 200lfm 400lfm LTM4623 4623f for more information www.linear.com/LTM4623
19 a pplica t ions i n f or m a t ion table 7. output voltage response vs component matrix (refer to figure 24) c in part number value c out1 part number value murata grm21br61e106ka73l 10f, 25v, 0805, x5r murata grm21br60j476me15 47f, 6.3v, 0805, x5r taiyo yuden tmk212bbj106kg-t 10f, 25v, 0805, x5r taiyo yuden jmk212bj476mg-t 47f, 6.3v, 0805, x5r murata grm31cr61c226me15l 22f, 25v, 1206, x5r taiyo yuden tmk316bbj226ml-t 22f, 25v, 1206, x5r v out (v) c in (ceramic) (f) c out1 (ceramic) (f) c ff (pf) v in (v) droop (mv) p-p derivation (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) freq (mhz) 1 10 47 100 5, 12 1 59 40 1 1 90.9 1 1.2 10 47 100 5, 12 1 59 40 1 1 60.4 1 1.5 10 47 100 5, 12 1 66 40 1 1 40.2 1 1.8 10 47 100 5, 12 1 75 40 1 1 30.1 1 2.5 10 47 100 5, 12 2 108 50 1 1 19.1 1 3.3 10 47 100 5, 12 3 111 60 1 1 13.3 2 5 10 47 100 12 5 156 60 1 1 8.25k 2 layout checklist/example the high integration of LTM4623 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessary . ? use large pcb copper areas for high current paths, including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? bring out test points on the signal pins for monitoring. figure 23 gives a good example of the recommended layout. table 5. 3.3v output, no heat sink derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 18, 19, 20 5, 12, 16 figure 10 0 none 25 figures 18, 19, 20 5, 12, 16 figure 10 200 none 22 figures 18, 19, 20 5, 12, 16 figure 10 400 none 22 table 6. 5v output, no heat sink derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 21, 22 12, 16 figure 11 0 none 25 figures 21, 22 12, 16 figure 11 200 none 22 figures 21, 22 12, 16 figure 11 400 none 22 LTM4623 4623f for more information www.linear.com/LTM4623
20 a pplica t ions i n f or m a t ion figure 23. recommended pcb layout figure 24. 4v in to 20v in , 1.5v output at 3a design figure 25. 2.375v in to 4v in , 1v output at 3a design with 800khz reduced frequency v in c out gnd v out 4623 f19 gnd c in v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin freq clkout v out 10f 25v 47f 4v v in 4v to 20v v out 1.5v 3a fb comp gnd 40.2k sgnd 4623 f20 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin clkout freq 5v v out 10f 6.3v 1.31m 1f 6.3v 47f 4v v in 2.375v to 4v v out 1v 3a fb comp gnd 90.9k sgnd 4623 f21 0.1f LTM4623 4623f for more information www.linear.com/LTM4623
21 a pplica t ions i n f or m a t ion v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin v out 10f 25v 2 47f 4v 2 20.1k v in 4v to 20v v out 1.5v 6a fb comp gnd 4623 f22 sgnd clkout freq 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin clkout freq v out fb comp gnd sgnd figure 26. 4v in to 20v in , two phases, 1.5v at 6a design figure 27. 4v in to 20v in , 1.2v and 1.5v with coincident tracking figure 28. 4v in to 20v in , 3.3v output with 2mhz external clock v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin v out 10f 25v 2 47f 4v 47f 4v 60.4k v in 4v to 20v v out 1.5v 3a v out2 1.2v 3a fb 40.2k comp gnd 60.4k 60.4k 4623 f23 sgnd freq clkout 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin v out fb comp gnd sgnd freq clkout v in sv in run intv cc mode phmode track/ss pgood LTM4623 clkin freq clkout v out 10f 25v 47f 6.3v v in 4v to 20v v out 3.3v 3a fb comp gnd 13.3k 161k 2mhz clock sgnd 4623 f24 0.1f LTM4623 4623f for more information www.linear.com/LTM4623
22 p ackage descrip t ion LTM4623 component lga pinout pin id function pin id function pin id function pin id function pin id function a1 comp a2 track/ss a3 run a4 freq a5 clkin b1 fb b2 phmode b3 gnd b4 sgnd b5 clkout c1 v out c2 pgood c3 gnd c4 mode c5 sv in d1 v out d2 v out d3 gnd d4 gnd d5 v in e1 v out e2 v out e3 gnd e4 intv cc e5 v in package row and column labeling may vary among module products. review each package layout carefully. LTM4623 4623f for more information www.linear.com/LTM4623
23 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 12345 pin 1 ?b (25 places) d e e b f g detail a 0.3175 0.3175 lga 25 0613 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? lga package 25-lead (6.25mm 6.25mm 1.82mm) (reference ltc dwg # 05-08-1949 rev ?) 7 see notes notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 25 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! detail b detail b substrate mold cap // bbb z z a symbol a b d e e f g h1 h2 aaa bbb eee min 1.72 0.60 0.27 1.45 nom 1.82 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 max 1.92 0.66 0.37 1.55 0.15 0.10 0.15 notes dimensions total number of lga pads: 25 h2 h1 s yx z? eee LTM4623 4623f for more information www.linear.com/LTM4623
24 ? linear technology corporation 2014 lt 1114 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTM4623 r ela t e d p ar t s p ackage p ho t o part number description comments ltm4625 higher current than LTM4623, bga package, taller but same footprint 5a, 4v < v in < 20v max ltm4619 dual 4a 4.5v < v in < 28v max , 15mm 15mm 2.82mm lga ltm4644 quad 4a configurable up to 16a, 4v < v in < 16v max , 9mm 15mm 5.01mm bga ltm4649 10a 4.5v < v in < 18v max , 9mm 15mm 4.92mm ltm8020 200ma, higher v in than ltm4625, same package footprint 4v < v in < 40v max , 6.25mm 6.25mm 2.32mm lga design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. LTM4623 4623f for more information www.linear.com/LTM4623

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